Case Studies/White Papers

Over 50 academic and research papers have been published referencing BEE system technology for a wide range of applications including: multi-core computer architecture, wireless communications, 100Gbps+ networking solutions, HD video processing, signal intelligence, radar/sonar array, bioinformatics, data mining, medical imaging, and more.

For an expanded list of publications, contact us.

Note: User will require an IEEE or ACM portal to access some of these pdfs

• ParaLearn: A Massively Parallel, Scalable System for Learning Interaction Networks on FPGAs, by Narges Bani Asadi, Garry P. Nolan and Wing H. Wong of Stanford University with John Wawrzynek, Christopher W. Fletcher and Greg Gibeling of University of California, Berkeley
  • Best Student Paper award at the ACM International Conference on Supercomputing (ICS'10): BEE-based collaboration with Stanford, led by John Wawrzynek and Garry Nolan, has won the Best Student Paper award at the ACM International Conference on Supercomputing (ICS'10) This effort utilized the BWRC Berkeley Emulation Engine to rapidly learn Baysean networks in systems biology, as described by Garry in a recent lunchtime seminar, and demonstrated at the last BWRC retreat.

 

• Base Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network, by Mingjie Lin and Yaling Ma of Stanford University, RECONFIG '09: Proceedings of the 2009 international conference on reconfigurable computing and FPGA's, December 2009

 

• Implementing a High-Performance Multi-threaded Microprocessor: A Case Study in High-Level Design and Validation, by Eric S. chung and James C. Hoe of Carnegie Mellon University, MEMOCODE '09: Proceedings of the 7th IEEE/ACM International conference on formal methods and models for co-design, July 2009.

 

• Internet-in-a-Box: Emulating Datacenter Network Architectures using FPGAs, by Jonathan D. Ellithorpe, Zhangxi Tan, and Randy Katz of University of California at Berkeley, DAC '09: Proceedings of the 46th annual Design Automation Conference, July 2009.

 

• ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs, by Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. hoe, Ken Mai and Babak Falsafi of Carnegie Mellon University, Transactions on Reconfigurable Technology and Systems (TRETS), Volume 2 Issue 2, June 2009.

 

• Performance and Power of Cache-Based Reconfigurable Computing, by Andrew Putnam, Susan Eggers, Dave Bennet, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan and Ralph Wittig of University of Washington in collaboration with Xilinx, ISCA '09: Proceedings of the 36th annual international symposium on computer architecture, June 2009.

 

• Accelerating Monte Carlo Based SSTA using FPGA, by Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zhou of University of California at Los Angeles.

 

• A Message-Passing Hardware/Software Co-Simulation Environment for Reconfigurable Computing Systems, by Manuel Saldana, Emanuel Ramalho and Paul Chow of University of Toronto, International Journal of Reconfigurable Computing, Volume 2009, January, 2009.

 

• A Multi-FPGA Application-Specific Architecture for Accelerating a Floating Point Fourier Integral Operator, by Jason Lee, Lesley Shannon, Matthew J. Yedlin, and Gary F. Margrave of Simon Fraser University of British Columbia and University of Calgary, ASAP '08: Proceedings of the 2008 international conference of application specific systems, architectures and processors, July 2008.

 

• RAMP: Research Accelerator for Multiple Processors, by John Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, James C. Hoe, Derek Chiou, and Krste Asanovic of University of California at Berkeley with University of Washington, Stanford University, Intel, Carnegie Mellon University, University of Texas, and the MAssachusetts Institute of Technology, IEE Micro, Volume 27 Issue 2, December 2007.