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Hardware
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BEE3 - SOC |
BEE3 - W |
BEE4 - SOC |
BEE4 - W |
miniBEE |
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BEE3 - WThe BEE3-W is a stackable, full speed multi-FPGA based prototyping platform integrated with DAC/ADC modules for mixed signal and digital communications designs.
Specifically designed to address rapid system level prototyping of wireless and digital communications designs, the BEE3-W is based on BEEcube's successful 3rd generation FPGA (Field Programmable Gate Array) Berkeley Emulation Engine (BEE).
The BEE3-W enables a wide range of high-performance, real time implementations in multiple military and defense applications. BEE3-W allows for flexible algorithm and feature set definitions and as a result excels as a true real-time development and deployment plaftorm for:
A single BEE3-W system consists of four Xilinx Virtex-5 FPGAs with a capacity of 5M ASIC gates, and the quad FPGA design is interconnected with a ring bus and integrated DDR2-667 memory. Each BEE3-W FPGA follows a symmetrical design, including identical memory and independent I/Os. Multiple high-speed data interfaces include: 160 Gbps SERDES, Quad x8 PCI Express, Quad 1000BASE-T Ethernet, and Quad 40-pair LVDS QSH expansion slots. The system has a capability of buffering 64GB of data in DDR2 memory.
The BEE3-W is integrated with a set ADC and DAC modules. The ADC module has an option of dual channel 3 GSps ADCs with independent clock, data, reset and trigger SMA inputs for each ADC, or a quad channel 1.5 GSps version. The 3Gps boards support 8-bit sampling resolution per channel per ADC/FPGA. The supported analog sample rates range from 1000 to 3000 MHz. The DAC module is a dual 2 GSps model which supports independent clock inputs and data outputs. The sampling resolution can be configured for either 9 bits up to 2 GSps (with a 4:1 mux) or 12 bits up to 1.5 Gsps (with a 2:1 mux).
Configuration and Hardware Options:BEE3 Virtex-5 LX155T-2C Configurations
BEE3 Virtex-5 Sx95T-2C Configurations
BEE3 Hardware Options
BEE3 - SOCThe BEE3-SOC is perfectly suited as a real world, real time prototyping and development platform. BEE3-SOC is a true high-speed multiple FPGA and validation solution designed to target:
Using the Xilinx 65nm FPGA family, each 2U rack mount BEE3 module consists of four large Virtex-5 LXT/SXT/FXT FPGA chips, along with up to 64GB DDR2 ECC DRAM and eight 10GigE interfaces for inter-module communication. In addition, up to 4 PCI Express x8 connections allow a maximum of 16GB per second, full-duplex data communication between each BEE3 module and computer host servers. At a power consumption of less than 400 watts, each BEE3 module can provide over 4 trillion integer operations per second, or emulate over 64 RISC processor cores concurrently at a 100MHz rate.
BEE3 Key Features:
Configuration and Hardware Options:BEE3 Virtex-5 LX155T-2C Configurations
BEE3 Virtex-5 Sx95T-2C Configurations
BEE3 Hardware Options
BEE4 - WBEE4-W is the newest generation of BEEcube's successful BEE (Berkeley Emulation Engine) hardware platforms. The BEE4-W is the ultimate mixed signal, full-speed FPGA prototyping platform. The BEE4-W is a commercial, stackable full speed multi-FPGA based prototyping platform, integrated with DAC/ADC modules for mixed signal and digital communications designs. The BEE4-W enables a wide range of high-performance, real-time implementations in multiple military and defense applications. BEE4-W allows for flexible algorithm and feature set definitions and as a result excels as a true real-time development and deployment platform for:
A single BEE4-W system consists of four Xilinx Virtex-6 FPGAs with a maximum capacity of 20M ASIC gates, and the quad FPGA design is interconnected with a ring bus and integrated DDR3-800/1066 memory. Each BEE4 FPGA follows a symmetrical design, including identical memory and independent I/Os. Multiple high-speed data interfaces include: 160 Gbps QSFP+, x8 Gen2 PCI Express, Quad 1000BASE-T Ethernet, and Quad FMC expansion slots. The system has a capability of buffering 128GB of data in DDR3 memory. The BEE4-W can be integrated with 4 sets of ADC and DAC modules combinations via BEE4-W's available FMC slots. BEEcube now offers an optional FMC DAC/ADC Module. Up to 4 sets of a single width FMC mezzanine card providing both a 12-bit, 2.3- GSps multi-Nyquist digital-to-analog converter and a 12 Bit, 1-GSps analog-to digital converter can be integrated with the standard BEE4-W. Parts used are the Maxim MAX19692 and Texas Instruments ADS5400. BEE4-W comes with, or can be bundled, with our unique:
BEE4-W Capabilities Include:
BEE4-W Features Include:
Configuration and Hardware Options:
Hardware Options
BEE4 - SOCBEE4-SOC is the ultimate full-speed FPGA prototyping platform. As a 4th generation BEE, the BEE-4 SOC's design is a result of 150 BEE systems used worldwide and over 10 years of research.
BEE4-SOC is perfect for both high-speed RTL verification and real data rate system integration validation. With its uniquoe capabilites and features, BEE4 directly addresses:
Each BEE4-SOC module consists of 4 FPGAs based on a unique HPC (High Performance Computing) architecture. BEE4-SOC modules can be stacked or clustered to increase capacity without losing speed. Depending on the design, users can run prototype logic up to 500 MHz and digital interface communication at 640 Gbps per BEE4-SOC module, including optical interfaces and multiple Digital to Analog and Analog to Digital Components. BEE4-SOC supports the latest FMC and QSPF+ interface standards. BEE4-SOC modules support of a variety of high-end Virtex 6 FPGAs, including LXT 240/365/550 and SXT 315/475, allowing BEE4 to support 20 MGate designs per module, or 400 MGates per rack. BEE4-SOC Capabilities Include:
BEE4-SOC Features Include:
Configuration and Hardware Options:
Hardware Options
miniBEEThe miniBEE is the ultimate full-speed mixed signal FPGA prototyping platform made portable. miniBEE offers application flexibility and customization as well as significant throughput capacity in a smaller footprint. miniBEE replaces standalone Test, PC, FPGA and Networking Switch/Router equipment. miniBEE can be an “all-in-one” oscilloscope, logic analyzer, spectrum analyzer, signal/pulse generator and arbitrary waveform generator.
miniBEE, targets applications like:
miniBEE Capabilities Include:
miniBEE Features Include:
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Software
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BPS 3.6 |
BPS 4.0 |
BPS - Lite |
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BPS 3.6With the availability of BEE3-W, BPS 3.6 adds several new components to the existing list of BPS supported hardware/software interfaces. Support is now included for the full range of ADC and DAC modules, which allow users to capture and create real-world analog signals directly within the BPS environment. The inter-FPGA communication interfaces on all BEE3 systems, including BEE3-W, have also been greatly enhanced by the new High Speed I/O component, which provides data transmission speeds up to DDR800 (double data rate signaling at 400MHz clock speed) between FPGAs. This version also adds support for dual-channel DRAM on all BEE3 models, which doubles the amount of memory bandwidth and addressable memory capacity available to each FPGA in the system. In addition, support for DRAM-based video frame buffers has also been added for all BEE3 based models as well as the Xilinx ML50x hardware platform, which delivers a wide range of possibilities in video capture, processing, and generation applications with support for frame buffers up to 4GB in size. Options: Available as an annual or perpetual software license. Single node-lock seat.
About BPS: BEEcube Platform Studio (BPS) is a system-level, hardware/software co-development environment on top of the MathWorks™ Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers. Months of engineering tasks to convert complex DSP algorithms to implementation can be achieved in a matter of days, all without requiring user knowledge of the low level FPGA implementation details, such as high speed I/O interfaces, timing closure, HW/SW interfaces, and IP integration issues. Each BPS platform is a collection of hardware devices and associated software available on the physical module. The BPS platform has been purposefully built to abstract hardware specific details away from the end user. The smallest unit of the BPS platform is a single FPGA. A typical design in the BPS design environment starts with the core algorithm design in Simulink with Xilinx System Generator for DSP. From the end-user perspective, Simulink designs only exist in a protected sandbox with the synchronous data flow execution model; all connections outside the core algorithm are virtually mapped through BPS interface block sets. A processor core, either in the form of a hard core (PowerPC 405) or a soft core (MicroBlaze™ processor), is implicitly included in all BPS designs. The processor core can communicate with the user XSG design through software registers, FIFO, or shared memory. Users can specify the desired communication method by selecting the corresponding BPS blocks in Simulink. All external network, I/O, and memory devices are abstracted into Simulink data sources or sinks, with a simple FIFO abstraction. BPS 4.0BPS 4.0 adds support for the latest Xilinx toold and devices including: Xilinx System Edition 12 and the Virtex-6 family of FPGAs. Supported hardware platforms include the Xilinx ML506 Evaluation Kit and BEEcube's own BEE4 system, in addition to a number of FMC expansion boards available for both platforms. More about BPS: BEEcube Platform Studio (BPS) is a system-level, hardware/software co-development environment on top of the MathWorks™ Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers. Months of engineering tasks to convert complex DSP algorithms to implementation can be achieved in a matter of days, all without requiring user knowledge of the low level FPGA implementation details, such as high speed I/O interfaces, timing closure, HW/SW interfaces, and IP integration issues. Each BPS platform is a collection of hardware devices and associated software available on the physical module. The BPS platform has been purposefully built to abstract hardware specific details away from the end user. The smallest unit of the BPS platform is a single FPGA. A typical design in the BPS design environment starts with the core algorithm design in Simulink with Xilinx System Generator for DSP. From the end-user perspective, Simulink designs only exist in a protected sandbox with the synchronous data flow execution model; all connections outside the core algorithm are virtually mapped through BPS interface block sets. A processor core, either in the form of a hard core (PowerPC 405) or a soft core (MicroBlaze™ processor), is implicitly included in all BPS designs. The processor core can communicate with the user XSG design through software registers, FIFO, or shared memory. Users can specify the desired communication method by selecting the corresponding BPS blocks in Simulink. All external network, I/O, and memory devices are abstracted into Simulink data sources or sinks, with a simple FIFO abstraction. BPS LiteBPS-Lite is part of BEEcube's Academic Program that strives to make the latest FPGA based computer systems available to higher education and research communities on a whole range of application domains. BPS-Lite software provides an accelerated design flow dramatically easing the use of Xilinx FPGAs and making FPGA design more accessible to developers, students, and academic researchers. BPS-Lite is available for us on the Xilinx XUPV5-LX110T single FPGA platform optimized for teaching and research purposes. BPS can also be used to develop software for applications for BEEcube's BEE3 high-end four FPGA systems, or for combinations of FPGA platforms, including clusters of multiple BEE3s. BPS-Lite is distributed free to universities worldwide. More about BPS: BEEcube Platform Studio (BPS) is a system-level, hardware/software co-development environment on top of the MathWorks™ Simulink® framework. BPS provides automatic generation of all platform specific hardware interfaces and corresponding software drivers. Months of engineering tasks to convert complex DSP algorithms to implementation can be achieved in a matter of days, all without requiring user knowledge of the low level FPGA implementation details, such as high speed I/O interfaces, timing closure, HW/SW interfaces, and IP integration issues. Each BPS platform is a collection of hardware devices and associated software available on the physical module. The BPS platform has been purposefully built to abstract hardware specific details away from the end user. The smallest unit of the BPS platform is a single FPGA. A typical design in the BPS design environment starts with the core algorithm design in Simulink with Xilinx System Generator for DSP. From the end-user perspective, Simulink designs only exist in a protected sandbox with the synchronous data flow execution model; all connections outside the core algorithm are virtually mapped through BPS interface block sets. A processor core, either in the form of a hard core (PowerPC 405) or a soft core (MicroBlaze™ processor), is implicitly included in all BPS designs. The processor core can communicate with the user XSG design through software registers, FIFO, or shared memory. Users can specify the desired communication method by selecting the corresponding BPS blocks in Simulink. All external network, I/O, and memory devices are abstracted into Simulink data sources or sinks, with a simple FIFO abstraction. | ||||
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Specialized Solutions
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BEEcube Design Services |
Specialized Products |
OpenSPARC |
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Specialized ProductsThe MORPH VITA 46 The MORPH VITA 46 is a board-level product based on reconfigurable logic. Intended for high-end signal processing and I/O applications, this VPX 1" pitch design features one Freescale MPC8641D High-performance Dual Core Processor and three Xilinx Virtex-5® XC5VSX95T FPGA devices. The FPGA array is interconnected via low power Serializer/Deserializer (SerDes) GTPs. The processor and FPGAs are interconnected via a Serial RapidIO switch and allows external communication to the four x4-lane Serial RapidIO ports out the P1 connector. Freescale's processor features dual 1GHz e600 32-bit PowerPC cores supporting the AltiVec instruction set. Two 512Mbyte DDR2 SDRAM banks, upgradeable to 1Gbyte, are available to the processor. Each XC5VSX95T features a massive programmable logic array, including over 58,000 flip-flops and their associated combinatorial logic. Additional embedded functions include 640 25x18 multipliers, 8.7Mb of Block RAM, 16 GTPs, and sophisticated digital clock management. Each FPGA has access to dedicated memory resources which includes 256MByte of 200MHz DDR2 SDRAM and 4MByte of 166MHz QDR2 SRAM. The XC5VSX95T is footprint compatible with other Virtex-5 devices in an FF1136 package that supports 640 I/O and 16 GTPs, allowing a wide range in versatility for user requirements and applications. The XMC site is a standard PCIe x8 site designed to enhance MORPH's reconfigurable capabilities with a wide variety of COTS functions such as A/Ds, high-speed I/O, and auxiliary processors/RAM. Applications
Download the Data Sheet for more information about the MORPH VITA 46 V2Pro Family The MORPH V2P product line is based on reconfigurable board level logic. Intended for high-end signal processing and I/O applications, MORPH features Xilinx Virtex-II Pro® devices. MORPH products are available in four different varieties. The MORPH VH and VL offer a single-slot 6U-160 VME64x, the MORPH PH is a single-slot 64-bit universal PCI, and the Morph PMC is a PCI Bus Mezzanine Card (PMC) design. Download the Data Sheet for more information about the MORPH V2Pro Family BEEcube Design ServicesBEEcube's highly experienced Design Services team extends the capabilities of BEEcube hardware and software solutions to meet developers' most demanding system requirements. We offer a wide range of capabilities and expertise to developers looking to complement the features of BEEcube's standard product range. These design service engagements vary from specific application development to companywide design framework solutions. In each instance, BEEcube works closely with you to create the best customer success in a minimal amount of time. Benefits of using BEEcube Design Services:
Two-Day Training: Two-day on-site instructor led training. Two-Week Support: Two-week engineering support for hardware system set-up, software installation, and initial application development. OpenSPARC on BEE3The BEE3 hardware platform is the ideal emulation and validation engine for designers who are interested in developing harware or software applications based on the OpenSPARC T1 core, the world's first freely-available 64-bit CMT microporcessor. As part of a joint development effort with Sun Microsystems and Xilinx, BEEcube is proud to offer support for the BEE3 platform as of the 1.7 OpenSPARC T1 hardware release. OpenSPARC development on BEE3 enables designers to reach significantly higher levels of performance and memory capacity than were previously available using single-FPGA evaluation boards alone. A single BEE3 module is capable of emulating a SPARC multi-core CMT system featuring:
For more information on the OpenSPARC project, click here.
For more information on Xilinx and the Xilinx University program, click here.
For current OpenSPARC on BEE3 developers, the latest Xilinx EDK IP cores and drivers for BEE3 can be downloaded. Click here for download.
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